1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package having a strengthening layer and a fabrication method thereof.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
In a flip-chip packaging process, a big CTE (Coefficient of Thermal Expansion) mismatch between a chip and a substrate adversely affects the formation of joints between conductive bumps of the chip and corresponding contacts of the substrate and easily causes delamination of the conductive bumps from the substrate.
Further, along with increased integration of integrated circuits, the CTE mismatch between the chip and the substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the reliability of electrical connection between the chip and the substrate and resulting in failure of a reliability test.
Accordingly, a silicon interposer is provided between the substrate and the chip. Since the silicon interposer is close in material to the chip, the above-described drawbacks caused by a CTE mismatch can be effectively overcome.
FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1 having a silicon interposer. Referring to FIG. 1, the semiconductor package 1 has a substrate 10; a silicon interposer 11 disposed on the substrate 10 through a plurality of solder balls 12; a UBM (Under Bump Metallurgy) layer 13 formed on the silicon interposer 11; and a chip 14 disposed on the silicon interposer 11 through a plurality of solder balls 15.
The substrate 10 has a first surface 10a having a plurality of bonding pads 101 and a second surface 10b opposite to the first surface 10a and having a plurality of bonding pads 102.
The silicon interposer 11 has a bottom surface 11a and an opposite top surface 11b. Further, the silicon interposer 11 has a first circuit layer 111 formed on the bottom surface 11a, a second circuit layer 112 formed on the top surface 11b, and a plurality of through silicon vias (TSVs) 113 penetrating the bottom surface 11a and the top surface 11b and electrically connecting the first circuit layer 111 and the second circuit layer 112. Furthermore, a first insulating layer 114 is formed on the bottom surface 11a and the first circuit layer 111 and a second insulating layer 115 is formed on the top surface 11b and the second circuit layer 112.
The silicon interposer 11 is disposed on the substrate 10 with the solder balls 12 electrically connecting the substrate 10 and the first circuit layer 111. The UBM layer 13 is formed on the second circuit layer 112. The chip 14 has a plurality of bonding pads 141 that are electrically connected to the second circuit layer 112 through the solder balls 15 and the UBM layer 13.
The semiconductor package 1 overcomes the above-described drawbacks and has a reduced size. For example, a substrate generally has a minimum line width/pitch of 12/12 um. When the I/O count of a semiconductor chip increases, since the line width/pitch of the substrate cannot be reduced, the area of the substrate must be increased such that more traces can be formed on the substrate and electrically connected to the semiconductor chip having high I/O count. On the other hand, referring to FIG. 1, the chip 14 is disposed on the silicon interposer 11 having TSVs 113 and electrically connected to the substrate 10 through the silicon interposer 11. Through a semiconductor process, the silicon interposer 11 can have a line width/pitch of 3/3 um or less. Therefore, the area of the silicon interposer 11 is sufficient for electrical connection with the chip 14 having high I/O count and hence the area of the substrate 10 does not need to be increased. Further, the fine line width/pitch of the silicon interposer 11 facilitates to shorten the electrical transmission path. Therefore, the semiconductor chip 14 disposed on the silicon interposer 11 achieves a higher electrical transmission speed than if being directly disposed on the substrate 10. However, the semiconductor package 1 having the silicon interposer 11 has a high fabrication cost. Accordingly, Si substrate interconnection technology has been developed to fabricate packages that do not include silicon interposers and have a size less than the semiconductor package 1.
FIGS. 2A to 2E are schematic cross-sectional views showing a semiconductor package 2 and a fabrication method thereof according to the prior art.
Referring to FIG. 2A, a carrier 20 and a circuit structure 21 are provided. The carrier 20 has a first surface 20a and a second surface 20b opposite to the first surface 20a. The circuit structure 21 has a first bottom surface 21a and a first top surface 21b opposite to the first bottom surface 21a. The circuit structure 21 has at least a dielectric layer 211, a plurality of conductive vias 212 formed in the dielectric layer 211, and at least a circuit layer 213 and a plurality of conductive pads 214 formed on the dielectric layer 211.
Further, a first insulating layer 22 is formed on the first bottom surface 21a and a second insulating layer 23 is formed on the first top surface 21b. The carrier 20 is disposed on the first insulating layer 22 via the second surface 20b thereof, and a UBM layer 24 is formed on the conductive pads 214.
Referring to FIG. 2B, at least a chip 25 is provided, which has an active surface 25a with a plurality of bonding pads 251 and an inactive surface 25b opposite to the active surface 25a. The chip 25 is disposed on the UBM layer 24 through a plurality of solder balls 26.
Referring to FIG. 2C, an underfill 27 is formed between the chip 25 and the second insulating layer 23.
Referring to FIG. 2D, an encapsulant 28 is formed on the second insulating layer 23. The encapsulant 28 has a second bottom surface 28a and a second top surface 28b opposite to the second bottom surface 28a. 
Referring to FIG. 2E, the encapsulant 28 is thinned from the second top surface 28b thereof by mechanical grinding. Then, subsequent process such as thinning and etching of the carrier 20 can be performed.
In the above-described method of the semiconductor package 2, the encapsulant 28 is thinned to reduce warping of the encapsulant 28 caused by a big CTE mismatch between the encapsulant 28 (or underfill 27) and the chip 25. Even further, the inactive surface 25b of the chip 25 can be exposed from the encapsulant 28 to improve the heat dissipating effect. However, the thinning process cannot effectively reduce warping of the encapsulant 28. Consequently, cracking of the chip 25 easily occurs.
Therefore, there is a need to provide a semiconductor package and a fabrication method thereof so as to overcome the above-described drawbacks.